DIRECTO=DISABLED, DIRECTI=DISABLED, UPLIMOFF=NORMAL_MODE, BANDSEL=SSCG_CONTROL, BYPASS=DISABLED, BYPASSCCODIV2=DIVIDE_BY_2
PLL control
| SELR | Bandwidth select R value |
| SELI | Bandwidth select I value |
| SELP | Bandwidth select P value |
| BYPASS | PLL bypass control 0 (DISABLED): Disabled. PLL CCO is used to create the PLL output. 1 (ENABLED): Enabled. PLL is bypassed, the PLL input clock is routed directly to the PLL output (default). |
| BYPASSCCODIV2 | Bypass feedback clock divide by 2. 0 (DIVIDE_BY_2): Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide. 1 (BYPASS): Bypass. The CCO feedback clock is divided only by the programmed M divide. |
| UPLIMOFF | Enable spread spectrum/fractional mode 0 (NORMAL_MODE): Normal mode. 1 (SSGC_MODE): SSGC mode. Spread spectrum/fractional mode. |
| BANDSEL | PLL filter control. Set this bit to one when the SSGC is disabled or at low frequencies. 0 (SSCG_CONTROL): SSCG control. The PLL filter uses the parameters derived from the SSCG decoder. 1 (MDEC_CONTROL): MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants. |
| DIRECTI | PLL0 direct input enable 0 (DISABLED): Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. 1 (ENABLED): Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO. |
| DIRECTO | PLL0 direct output enable 0 (DISABLED): Disabled. The PLL output divider (P divider) is used to create the PLL output. 1 (ENABLED): Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |